Semiconductor memory device

ABSTRACT

A semiconductor memory device comprises: a memory cell array including a plurality of word lines, a plurality of bit line pairs containing a first bit line and a second bit line, and a plurality of memory cells; a plurality of replica bit lines formed in the same manner as the first and second bit lines; a write buffer circuit operative to drive the first or second bit line to the ground voltage; a replica write buffer circuit operative to drive the replica bit lines to the ground voltage; and a boot strap circuit operative to drive the first or second bit line currently driven to the ground voltage further to a negative potential at a timing when the potential on the replica bit lines reaches a certain value.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority fromprior Japanese Patent Application No. 2009-063575, filed on Mar. 16,2009, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device, and moreparticularly to a semiconductor memory device operable on low voltage,such as an SRAM (Static Random Access Memory).

2. Description of the Related Art

An LSI used in mobile instruments is required to reduce the powerconsumption to extend the battery-driven time. Lowering the supplyvoltage is effective to reduce the power consumption. An increase incharacteristic dispersion among elements due to the progression ofscaling in recent years, however, reduces the operational margin of theSRAM used in the LSI and makes it difficult to lower the operatingvoltage of the SRAM. The operating voltage of the SRAM defines thesupply voltage of the LSI and accordingly makes it difficult to lowerthe supply voltage of the entire LSI. Operation of the SRAM on lowersupply voltage deteriorates the write characteristic of the SRAM as aproblem.

To deal with this problem, a method has been proposed, which comprisesshifting one of two bit lines connected to an SRAM cell to a negativepotential on writing (see K. Nii et al., “A 45-nm Single-port andDual-port SRAM family with Robust Read/Write Stabilizing Circuitry underDVFS Environment”, 2008 Symposium on VLSI Circuits Digest of TechnicalPapers, P 212-213) When a boot strap circuit is used to shift one of thebit lines to the negative potential, a gate-source voltage of a transferNMOS transistor in the SRAM cell can be boosted, thereby improving thewrite characteristic of the SRAM.

The use of the boot strap circuit to shift the bit line to the negativepotential on writing, however, causes the following problem. The timingof shifting the bit line to the negative potential by the boot strapcircuit and the level of the negative potential applied to the bit linevary depending on the capacitance of the bit line and so forth. A numberof SRAMs having different word line lengths and bit line lengths areused inside the LSI. The bit lines having different bit line lengthsdiffer from each other in bit line capacitance. Therefore, the timing ofshifting the bit line to the negative potential and the level of thenegative potential applied to the bit line may vary and deteriorate thecharacteristic of writing data to the SRAM possibly.

SUMMARY OF THE INVENTION

In an aspect the present invention provides a semiconductor memorydevice, comprising: a memory cell array including a plurality of wordlines, a plurality of bit line pairs containing a first bit line and asecond bit line intersecting the word lines, and a plurality of memorycells connected at the intersections of the plurality of word lines andthe plurality of bit line pairs; a plurality of replica bit lines formedin the same manner as the first and second bit lines; a write buffercircuit operative to drive the first or second bit line to the groundvoltage on writing data to the memory cell; a replica write buffercircuit operative to drive the replica bit lines to the ground voltageby substantially the same driving force as that of the write buffercircuit; and a boot strap circuit operative to drive the first or secondbit line currently driven to the ground voltage further to a negativepotential at a timing when the potential on the replica bit linesreaches a certain value.

In another aspect the present invention provides a semiconductor memorydevice, comprising: a memory cell array including a plurality of wordlines, a plurality of bit line pairs containing a first bit line and asecond bit line intersecting the word lines, and a plurality of memorycells connected at the intersections of the plurality of word lines andthe plurality of bit line pairs; a write buffer circuit operative todrive the first or second bit line to the ground voltage on writing datato the memory cell; and a boot strap circuit operative to drive thefirst or second bit line currently driven to the ground voltage furtherto a negative potential at a certain timing, wherein the boot strapcircuit includes a potential control circuit operative to vary the valueof the negative potential applied to the first or second bit line inaccordance with the voltage value of the supply voltage, wherein thepotential control circuit makes the negative potential larger in thenegative direction as the voltage value of the supply voltage descends.

In yet another aspect the present invention provides a semiconductormemory device, comprising: a memory cell array including a plurality ofword lines, a plurality of bit line pairs containing a first bit lineand a second bit line intersecting the word lines, and a plurality ofmemory cells connected at the intersections of the plurality of wordlines and the plurality of bit line pairs; a write buffer circuitoperative to drive the first or second bit line to the ground voltage onwriting data to the memory cell; a boot strap circuit operative to drivethe first or second bit line currently driven to the ground voltagefurther to a negative potential at a certain timing; and a voltage sensecircuit operative to sense if the voltage value of the supply voltage islower than a certain voltage value to provide a control signal forcontrolling operation of the boot strap circuit, wherein the boot strapcircuit drives the first or second bit line to the negative potential,based on the control signal, if the voltage value of the supply voltageis lower than the certain voltage value.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing a configuration of a semiconductormemory device according to a first embodiment.

FIG. 2 is a circuit diagram showing a memory cell of the 6-transistortype in the semiconductor memory device according to the firstembodiment.

FIG. 3 is a waveform diagram of the bit line potential on writing in thesemiconductor memory device.

FIG. 4 is a waveform diagram on writing in the semiconductor memorydevice according to the first embodiment.

FIG. 5 is a graph showing a relation between the data line capacitanceand the bit line potential in the semiconductor memory device accordingto the first embodiment.

FIG. 6 is a circuit diagram showing a configuration of a semiconductormemory device according to a second embodiment.

FIG. 7 is a graph showing a relation between the process condition andthe bit line potential in the semiconductor memory device according tothe second embodiment.

FIG. 8 is a circuit diagram showing a configuration of a semiconductormemory device according to a third embodiment.

FIG. 9 is a circuit diagram showing a configuration of a semiconductormemory device according to a fourth embodiment.

FIG. 10 is a graph showing a relation between the supply voltage and thebit line potential in the semiconductor memory device according to thefourth embodiment.

FIG. 11 is a block diagram showing a configuration of a semiconductormemory device according to a fifth embodiment.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The embodiments associated with the semiconductor memory deviceaccording to the present invention will now be described in detail withreference to the drawings.

First Embodiment

FIG. 1 is a circuit diagram showing a configuration of a semiconductormemory device according to a first embodiment of the present invention.FIG. 2 is a circuit diagram showing the details of an SRAM cell shown inFIG. 1. FIG. 1 shows a circuit used in controlling the bit line voltageon writing to the SRAM cell.

[Configuration]

The semiconductor memory device according to the present embodimentcomprises a memory cell array 1, and a write buffer circuit 4 operativeto selectively drive a bit line pair BL connected to an SRAM cell SC inthe memory cell array 1. The semiconductor memory device also comprisesa replica write buffer circuit 2 and a boot strap circuit 3 foradjusting the timing of applying a voltage to the bit line pair BL onwriting and the value of the voltage applied to the bit line pair BL.Although not shown in FIG. 1, the semiconductor memory device maycomprise a row decoder operative to select a word line, and a controlleroperative to control these circuits.

The memory cell array 1 includes a plurality of word lines WL, aplurality of bit line pairs BL of bit lines BLt, BLc, and a plurality ofSRAM cells SC connected at the intersections of the word lines WL andthe bit line pairs BL. The SRAM cell SC is a memory cell of the6-transistor type as shown in FIG. 2. Namely, the memory cell of the6-transistor type includes a first inverter IV1 containing a PMOStransistor Q1 and an NMOS transistor Q2 connected in series and havingsources connected to the supply line VDD and the ground line VSS,respectively, and a second inverter IV2 containing a PMOS transistor Q3and an NMOS transistor Q4 connected in series and having sourcesconnected to the supply line VDD and the ground line VSS, respectively.These inverters IV1, IV2 have respective inputs and outputs mutuallycross-connected. Between the bit line BLt and the output terminal of thefirst inverter IV1, a first transfer transistor Q5 is connected. Betweenthe bit line BLc and the output terminal of the second inverter IV2, asecond transfer transistor Q6 is connected. The first and secondtransfer transistors Q5, Q6 have respective gate terminals connected tothe word line WL. Writing to the memory cell of the 6-transistor type isexecuted using both the bitlines BLt, BLc. In contrast, reading may besingle-ended reading executed from either of the bit lines BLt, BLc. Inthe present embodiment the bit lines BLt, BLc are assumed to have a bitline capacitance C_bl each.

As shown in FIG. 1, in the semiconductor memory device according to thepresent embodiment, two replica bit lines RBL having almost the samelength as the bit line pair BL are disposed. The bit line pair BL andthe replica bit lines RBL are connected to the supply line VDD toprecharge the bit line pair BL and the replica bit lines RBL via PMOStransistors Q18-Q21. The replica bit lines RBL are connected to thereplica write buffer circuit 2 via NMOS transistors Q8, Q9. In thepresent embodiment, the replica bit lines RBL are substantially same inlength as the bit line pair BL and disposed two. Therefore, the entireof the replica bit lines RBL has double the capacitance of the bit lineBLt or the bit line BLc.

The replica write buffer circuit 2 includes a NAND gate G1, a NOR gateG2 and an NMOS transistor Q7. The gate G1 receives a write enable signalWE. The gate G1 has an output terminal connected to the gate terminal ofthe transistor Q7 via the gate G2. The replica bit lines RBL areconnected to the ground line VSS via the transistor Q7. The replicawrite buffer circuit 2 has a function of driving the precharged replicabit lines RBL to the ground voltage, based on the write enable signalWE.

The replica bit lines RBL are connected to a plurality of invertersIV3-IV5 in series. The potential on the replica bit lines RBL isprovided as a boost enable signal boost_en, via the inverters IV3-IV5.The inverters IV3-IV5 have a circuit threshold, which is set almost halfthe voltage value of the supply voltage VDD. Namely, the invertersIV3-IV5 have a function of inverting the output signal, that is, theboost enable signal boost_en from “L” to “H” when the voltage on thereplica bit lines RBL descends from the precharged voltage VDD to around½ the voltage VDD. The inverter IV5 has an output terminal connected viaan inverter IV6 to the boot strap circuit 3 and the write buffer circuit4.

The boot strap circuit 3 includes inverters IV7-IV10, transistorsQ10-Q13 and a boot-strap capacitor C_boost. The inverter IV6 has anoutput terminal connected via the inverters IV7-IV8 to a node A at oneend of the capacitor C_boost. The other end of the capacitor C_boost isdefined as a node N. Between the node A and the node N, the PMOStransistor Q10 and the NMOS transistor Q11 are connected in parallelwith the capacitor C_boost. The transistor Q10 has a gate terminal,which receives the write enable signal WE via the inverters IV9, IV10.The transistor Q11 has a gate terminal, which receives the write enablesignal WE via the inverter IV9. The node N is connected to the groundline VSS via the NMOS transistors Q12, Q13 for discharging the node N.The transistor Q12 has a gate terminal, which receives the boost enablesignal boost_en via the inverter IV6. The transistor Q13 has a gateterminal, which receives the write enable signal WE via the invertersIV9, IV10. The boot strap circuit 3 has a function of shifting thepotential on the node N to a negative potential on execution of writing,and then applying the negative potential on the node N to the bit linepair BL via the write buffer circuit 4 to drive either of the bit lineBLt or BLc to the negative potential, as described later.

The write buffer circuit 4 includes an inverter IV11, NMOS transistorsQ14-Q17, NAND gates G3, G4 and NOR gates G5-G8. The gate G3 receives thewrite enable signal WE and a data signal DI. The gate G4 receives thewrite enable signal WE and the data signal DI via the inverter IV11. Thegate G3 has an output terminal connected to the gates G5, G6. The gateG4 has an output terminal connected to the gates G7, G8. The gates G5,G8 have input terminals, which receive the boost enable signal boost_envia the inverter IV6. The gates G6, G7 have input terminals, whichreceive the boost enable signal boost_en. The gates G5-G8 have outputterminals connected to the gate terminals of the transistors Q14-Q17,respectively.

The bit lines BLt, BLc in the memory cell array 1 are connected to thewrite buffer circuit 4 via NMOS transistors Q22, Q23. The transistorsQ22, Q23 are controlled to turn on/off by a column selection signal CSfed to the gate terminals. The bit lines BLt, BLc are connected to theground line VSS via the transistors Q15, Q16 in the write buffer circuit4. The bit lines BLt, BLc are also connected to the node N in the bootstrap circuit 3 via the transistors Q14, Q17 in the write buffer circuit4. The write buffer circuit 4 has a function of discharging either ofthe pair of bit lines BL to 0 V in accordance with write data at thestart of writing. The replica write buffer circuit 2 and the writebuffer circuit 4 both use NMOS transistors to drive the replica bitlines RBL and the bit line pair BL to the ground voltage. These NMOStransistors can be formed through the same process to allow the replicabit lines RBL and the bit line pair BL to have almost the same drivingforce.

Prior to describing operation of the SRAM in the present embodiment, thefollowing description is made with reference to FIG. 3 on a problem thatmay arise on execution of writing to the SRAM cell SC while thepotential of one of the bit line pair BL is shifted to a negativepotential. FIG. 3 is a waveform diagram of the potential on the bit lineto which a negative potential is applied on writing in the semiconductormemory device.

On writing data to the SRAM cell SC, the word line WL is booted to turnon the transfer transistors Q5, Q6 in the SRAM cell SC. In addition, oneof the pair of bit lines BL is brought to the supply voltage VDD and theother to the negative potential using the boot strap circuit to feeddata to the inverters IV1, IV2 in the SRAM cell SC.

When it is intended to use the boot strap circuit to bring the bit lineBL to the negative potential on writing, the following problem mayoccur. In the boot strap circuit, after the beginning of data writing(after time t1 in FIG. 3), the boot strap circuit is activated at thetiming when the bit line BL to be brought to the negative potentialreaches 0 V, (time t2 after time t_boost shown in FIG. 3 elapsed), togenerate the negative potential applied to the bit line BL. At thistime, if the potential on the bit line BL does not descend sufficiently,the bit line BL cannot be brought to a sufficient negative potential. Ifa sufficient time is ensured (the time t_boost is made longer) to allowthe potential on the bit line BL to descend sufficiently, the time forthe entire of writing is made longer as a problem.

The SRAM cells SC in the memory cell array differ from each other in theword line length and the bit line length. The bit lines BL havingdifferent bit line lengths differ from each other in the bit linecapacitance and accordingly differ in time for the potential on the bitline BL to descend. The timing (time t2) of activating the boot strapcircuit may be set in accordance with the time for the potential on thebit line BL having the longest bit line length to descend. In this case,though, SRAM cells SC having shorter bit line lengths tend to haveexcessive timing margins.

The potential level V_boost of the negative potential generated at theboot strap circuit can be determined by the ratio between thecapacitance on the bit line BL and the capacitance inside the boot strapcircuit. A variation in the bit line length changes the capacitance onthe bit line BL and accordingly the potential level V_boost of thenegative potential generated at the boot strap circuit varies as aproblem. If the boot strap circuit is designed to generate a desirednegative potential V_boost in a configuration with the longest bit linelength, it generates negative potentials more than required for shorterbit line lengths. In this case, if the potential level on the bit lineBL descends excessively, in SRAM cells SC, which are connected to thesame bit line BL as the selected SRAM cell but associated word line WLare not selected, the gate-source voltage of the transfer transistorsQ5, Q6 may possibly exceed the threshold voltage and destruct data heldtherein. Further, writing to the selected SRAM cell may possibly supplythe transfer transistors Q5, Q6 with a higher potential than thebreakdown voltage thereof.

[Operation]

The following description is given to data writing with the use of thereplica write buffer circuit 2, the boot strap circuit 3 and the writebuffer circuit 4 of the present embodiment shown in FIG. 1. Prior towriting, a precharge signal/PC is first made “L” to precharge the bitline pair BL and the replica bit lines RBL via the transistors Q18-Q21.

At the beginning of writing, the write enable signal WE fed to thereplica write buffer circuit 2, the bootstrap circuit 3 and the writebuffer circuit 4 is made “H” at the same timing to operate thesecircuits. In addition, the selected word line WL is boosted to “H” toturn on the transfer transistors Q5, Q6 in the SRAM cell SC. The boostenable signal boost_en is still at “L” because the replica bit lines RBLare precharged to the supply voltage VDD.

The write buffer circuit 4 receives the write enable signal WE and theboost enable signal boost_en, on writing, as well as a data signal DIcorresponding to write data. The data signal DI is herein assumed at“H”. When the write enable signal WE and the data signal DI are at “H”,the gate G3 provides an output signal at “L”. In this case, the boostenable signal boost_en is at “L” and the gate G6 provides an outputsignal at “H”, which allows the bit line BLt to be discharged to 0 Vthrough the transistor Q15. On the other hand, the gate G4 provides anoutput signal at “H”, which allows the gates G7, G8 to provide outputsignals at “L” regardless of the state of the boost enable signalboost_en. This prevents the transistors Q16, Q17 from turning on andkeeps the bit line BLc on the precharged voltage VDD.

In the boot strap circuit 3, as the boost enable signal boost_en is at“L” before writing, the voltage VDD appears on the node A at one end ofthe capacitor C_boost via the inverters IV6-IV8. In addition, as thewrite enable signal WE is also at “L”, the node N at the other end isshort-circuited with the node A via the transistors Q10, Q11, and thusthe voltage VDD also appears thereon. When the write enable signal WE isturned to “H” to start writing, the transistors Q12, Q13 turn on todischarge the node N gradually. The transistors Q12, Q13 are set smallerin driving force than the transistors Q15, Q16 in the write buffercircuit 4 and the transistor Q7 in the replica write buffer circuit 4,and provided as a discharge circuit for the capacitor C_boost.

When the write enable signal WE is turned to “H”, the replica writebuffer circuit 2 turns on the transistor Q7 to start discharging thereplica bit lines RBL. When the voltage on the replica bit lines RBL isdischarged to around ½ the voltage VDD, the boost enable signal boost_enoutput from the inverters IV3-IV5 is inverted to “H”. As describedabove, the capacitance on the replica bit lines RBL is almost double thecapacitance of the bit line BLt. Monitoring the timing of dischargingthe replica bit lines RBL to around ½ the voltage VDD through thereplica write buffer circuit 2 makes it possible to monitor the timingof discharging the normal bit line BLt to almost 0 V regardless of thebit line length.

When the boost enable signal boost_en turns from “L” to “H”, in thewrite buffer circuit 4, the output signal from the gate G6 turns from“H” to “L” and the output signal from the gate G5 turns from “L” to “H”.As a result, the transistor Q15 turns off, and the transistor Q14connected to the node N in the boot strap circuit 3 turns on instead.

When the boost enable signal boost_en turns from “L” to “H”, in the bootstrap circuit 3, the potential on the node A turns from the supplyvoltage VDD to the ground voltage 0 V. At this time, the capacitivecoupling with the capacitor C_boost varies the potential on the node Nin the negative direction. If the node N has been discharged to 0 V, thecapacitive coupling with the capacitor C_boost brings the node N toaround a voltage, −VDD. Thereafter, in accordance with the ratio betweenthe capacitance C_bl on the bit line BLt and the capacitance on thecapacitor C_boost in the boot strap circuit 3, charges are redistributedto determine the potential level Vbl on the bit line BLt as representedby the following expression 1.Vbl=−VDD*C_boost/(C _(—) bl+C_boost)  [Expression 1]

If the capacitance of the capacitor C_boost is sufficiently smaller thanthe capacitance C_bl on the bit line BLt, the potential level Vbl on thebit line BLt can be briefly represented by the following expression 2.Vbl=−VDD*C_boost/C _(—) bl  [Expression 2]

Through the above operation, the bit line BLt of the bit line pair BL isbrought to the negative potential and the bit line BLc to the supplyvoltage VDD. In the SRAM cell SC targeted for data write, the transfertransistors Q5, Q6 are turned on. The potentials on the bit lines BLt,BLc are fed via the transfer transistors Q5, Q6 to the inverters IV1,IV2 in the SRAM cell SC to write data in the SRAM cell SC.

[Effect]

The effect on writing data to the SRAM cell SC in the semiconductormemory device of the present embodiment is described with reference toFIGS. 4 and 5. FIG. 4 shows operating waveforms in the SRAM according tothe present embodiment. FIG. 4 shows waveforms of potentials on the bitline BLt, the boost enable signal boost_en, and the node N on writing.FIG. 5 is a graph showing a relation between the bit line capacitanceand the bit line potential in the SRAM according to the presentembodiment. FIG. 5 shows variations in the negative potential Vbl on thebit line BLt on writing when the bit line capacitance is varied smallfrom 0.1 pF to 0.01 pF. The comparison example in FIG. 5 shows anexample in driving the boot strap circuit, on a base of the time for thebit line having the longest bit line length to surely descend to 0 V,without using the replica write buffer circuit 2 according to thepresent embodiment.

In writing data to the SRAM cell, as the variation in the length of thebit line makes the capacitance C_bl smaller, the bit line can bedischarged faster. In the SRAM of the present embodiment, the boostenable signal boost_en is controlled by the potential on the replica bitlines RBL having the capacitance corresponding to the bit line pair BL.Therefore, as shown in FIG. 4, even if the capacitance C_bl on the bitline BLt is made smaller to discharge the bit line BLt faster, the boostenable signal boost_en rises from “L” to “H” when the potential on thebit line BLt reaches almost 0 V. Thus, the SRAM of the presentembodiment makes it possible to achieve an optimal timing for varyingthe boost enable signal boost_en to operate the boot strap circuit.

The following consideration is given to the value of the negativepotential applied to the bit line when the bit line capacitance becomessmaller. As described before, if the bit line BLt has a capacitanceC_bl, the potential level Vbl on the bit line BLt is represented byVbl=−VDD*C_boost/C_bl.

It is herein assumed that the capacitance on the bit line BLt variesfrom C_bl to C_bl/2. In this case, the capacitance on the replica bitlines RBL configured to have double the capacitance on the bit line BLtalso becomes half. Therefore, it is possible to make earlier the timingof the boost enable signal boost_en rising from “L” to “H” when thereplica bit lines RBL are discharged. Thus, the length of discharge timefor the node N can be reduced. If the node N has been discharged toVDD/2, the capacitive coupling with the capacitor C_boost lowers thevoltage on the node N to around ½ the voltage −VDD. Thereafter, thepotential level Vbl on the bit line BLt becomes as represented by thefollowing expression 3.Vbl=(−VDD/2)*(C_boost/((C _(—) bl/2)+C_boost))  [Expression 3]

If the capacitance of the capacitor C_boost is sufficiently smaller thanthe capacitance C_bl/2 on the bit line BLt, the potential level Vbl onthe bit line can be briefly represented by the following expression 4.Vbl=−VDD*C_boost/C _(—) bl  [Expression 4]

This has the same value as the potential level Vbl represented by theexpression 2 in the case of the capacitance C_bl on the bit line BLt.Thus, even when the capacitance on the bit line BLt varies, the negativepotential applied to the bit line BLt can be made at the same potentiallevel. FIG. 4 shows that when the variation in capacitance on the bitline BLt makes earlier the timing of the boost enable signal boost_en tovary from “L” to “H”, the timing of the node N varying to the negativepotential also becomes gradually earlier. If the timing of the node Nvarying to the negative potential becomes earlier, the potential levelon the node N at that time ascends. As the capacitance on the bit lineBLt has varied, however, almost an identical negative potential can begenerated as the potential level finally applied to the bit line BLt.

In the SRAM of the comparison example shown in FIG. 5, the boot strapcircuit brings the bit line to a negative potential after the bit lineBL surely reaches 0 V. Therefore, the smaller the bit line capacitance,the larger the bit line potential varies to lower the negative potentialVbl applied to the bit line. On the other hand, in the SRAM of thepresent embodiment, even if the bit line capacitance C_bl varies, thevariation in the negative potential Vbl applied to the bit line issmaller.

As described above, the SRAM of the present embodiment uses the replicabit lines RBL to monitor the time for the potential on the bit line BLtto vary, which is fed back to the potential on the boot-strap capacitorC_boost in the boot strap circuit 3. Thus, even if the bit line lengthvaries, the timing of applying a negative potential to the bit line BLtand the level of the negative potential applied can be optimized. TheSRAM according to the present embodiment makes it possible to preventthe deterioration of the data write characteristic caused by thecapacitance on the data line and execute writing on low voltage.

Second Embodiment

A second embodiment of the present invention is described next withreference to FIG. 6 and so forth. FIG. 6 is a circuit diagram showing aconfiguration of a semiconductor memory device according to the secondembodiment of the present invention.

[Configuration]

In the semiconductor memory device according to the present embodimentthe parts having the same configurations as those in the SRAM of thefirst embodiment are denoted with the same reference numerals andomitted from the description. The SRAM according to the presentembodiment includes a dummy cell DC connected to the replica bit linesRBL, different from the first embodiment.

The dummy cell DC has the same configuration as the normal SRAM cell SCshown in FIG. 2. In the dummy cell DC the transfer transistors Q5, Q6have respective gates connected to a dummy word line DWL, different fromthe normal SRAM cell SC. FIG. 6 shows only one dummy cell DC thoughplural dummy cells are actually connected in parallel. In this case, thetransistors used in the dummy cell DC and the normal SRAM cell SC areformed through the same process steps to have almost the same thresholdvoltage.

[Operation]

The replica write buffer circuit 2, the boot strap circuit 3 and thewrite buffer circuit 4 of the present embodiment operate in the samemanner as in the first embodiment. In writing in the SRAM of the presentembodiment, the dummy word line DWL is boosted to “H” at the same timeas the timing when the normal selected word line WL is boosted to “H”.Once the dummy word line DWL is selected, the dummy cell DC dischargesthe replica bit lines RBL through the transfer transistors Q5, Q6 andNMOS transistors Q2, Q4. Namely, in the SRAM of the present embodiment,the replica bit lines RBL are discharged by the dummy cell DC and thereplica buffer circuit 2.

[Effect]

In discharge by the dummy cell DC, the threshold voltage of the NMOStransistor used in the dummy cell DC varies the rate of discharge fromthe replica bit lines RBL. Namely, the lower the threshold voltage ofthe NMOS transistor, the faster the potential on the replica bit linesRBL varies and the faster the state of the boost enable signal boost_envaries as well. On the other hand, the higher the threshold voltage ofthe NMOS transistor, the slower the potential on the replica bit linesRBL varies.

If the state of the boost enable signal boost_en varies faster, the bootstrap circuit 3 performs an operation while the potential on the node Ndoes not descend much and the potential level Vbl applied to the bitline BLt is elevated. If the state of the boost enable signal boost_envaries slower, the boot strap circuit 3 performs an operation after thepotential on the node N fully descends and the potential level Vblapplied to the bit line BLt becomes lower. The transistors used in thedummy cell DC and the SRAM cell SC have almost the same thresholdvoltage. Therefore, as a result, the lower the threshold voltage of theNMOS transistor in the SRAM cell SC, the higher the potential level Vblon the bit line BLt becomes. On the other hand, the higher the thresholdvoltage of the NMOS transistor, the lower the potential level Vbl on thebit line BLt becomes.

The state of the potential level Vbl is shown in FIG. 7. FIG. 7 is agraph showing a relation between the process condition (SRAM ProcessCorner) and the bit line potential in the SRAM according to the presentembodiment. The process condition on the SRAM is represented by theoperating speed based on the threshold voltage of the transistor.Namely, the threshold voltage of the transistor descends in order ofslow-slow (ss) typical-typical (tt), and fast-fast (ff), and theoperating speed becomes faster as shown. In the SRAM of the presentembodiment, the lower the threshold voltage of the transistor, thehigher the potential level Vbl on the bit line BLt becomes.

As described above, if the potential level Vbl on the bit line BLtdescends excessively, in SRAM cells SC, which are connected to the samebit line BLt as the selected SRAM cell but associated word line WL arenot selected, the gate-source voltage of the transfer transistors Q5, Q6may possibly exceed the threshold voltage and destruct data heldtherein. In the present embodiment, however, as shown in FIG. 7, thelower the threshold voltage of the NMOS transistor in the SRAM cell SC,the higher the negative potential applied to the bit line BLt becomesand nears 0 V. Thus, the lower the threshold voltage and the more easilydestructive the data in the SRAM cell becomes, the smaller the magnitudeof the negative potential applied to the bit line BLt becomes.Accordingly, it is possible to effectively prevent data destruction.

In general, the write characteristic of the SRAM cell SC depends on thethreshold voltage of the NMOS transistor used in the SRAM cell SC.Namely, the higher the threshold voltage, the worse the writecharacteristic becomes. In the present embodiment, however, if thethreshold voltage of the NMOS transistor is higher and the writecharacteristic is worse, the level of the negative potential Vbl appliedto the bit line descends. Accordingly, it is possible to improve thewrite characteristic. On the other hand, if the threshold voltage of theNMOS transistor is lower, the negative potential Vbl on the bit line BLtcan be controlled not to descend too much. Accordingly, it is possibleto suppress the power consumption in the SRAM.

Third Embodiment

A third embodiment of the present invention is described next withreference to FIG. 8 and so forth. FIG. 8 is a circuit diagram showing aconfiguration of a semiconductor memory device according to the thirdembodiment of the present invention.

[Configuration]

In the semiconductor memory device according to the present embodimentthe parts having the same configurations as those in the SRAM of thesecond embodiment are denoted with the same reference numerals andomitted from the description. The SRAM according to the presentembodiment differs from the second embodiment in configurations of theboot strap circuit 3 and the write buffer circuit 4.

The boot strap circuit 3 in the present embodiment includes invertersIV12-IV14, transistors Q24-Q28 and a boot strap capacitor C_boost. Theoutput terminal of the inverter IV5 is connected to the input terminalof the inverter IV12 to feed the boost enable signal boost_en thereto.The output terminal of the inverter IV12 is connected via the inverterIV13 to the gate terminals of the NMOS transistor Q24 and the PMOStransistor Q25. The PMOS transistor Q26 and the NMOS transistor Q27 haverespective gate terminals, which are supplied with the write enablesignal WE via the inverter IV14. The transistors Q24-Q26 are connectedin series between the supply line VDD and the groundline VSS. Theconnection portion between the transistors Q24 and Q25 is connected tothe node A at one end of the capacitor C_boost. The transistor Q27 isconnected between the node A and the ground line VSS. The node N isconnected to the ground line VSS via the NMOS transistor Q28. Thetransistor Q28 has a gate terminal, which is supplied with the boostenable signal boost_en via the inverter IV12.

The write buffer circuit 4 of the present embodiment includes invertersIV11, IV15, IV16, NMOS transistors Q29, Q30, and NAND gates G3, G4. Thegate G3 receives the write enable signal WE and the data signal DI. Thegate G4 receives the write enable signal WE and the data signal DI viathe inverter IV11. The gate G3 has an output terminal, which isconnected to the gate terminal of the NMOS transistor Q29 via theinverter IV15. The gate G4 has an output terminal, which is connected tothe gate terminal of the NMOS transistor Q30 via the inverter IV16. Thebit lines BLt, BLc in the memory cell array 1 are connected to theground line VSS via the transistors Q29, Q30 and the node N in the bootstrap circuit 3. The write buffer circuit 4 has a function of connectingeither of the pair of bit lines BL to the node N in the boot strapcircuit 3 in accordance with write data at the start of writing.

[Operation]

The following description is given to data writing with the use of thereplica write buffer circuit 2, the boot strap circuit 3 and the writebuffer circuit 4 of the present embodiment shown in FIG. 8.

The write buffer circuit 4 receives the write enable signal WE and theboost enable signal boost_en, on writing, as well as a data signal DIcorresponding to the write data. The data signal DI is herein assumed at“H”. When the write enable signal WE and the data signal DI are at “H”,the gate G3 provides an output signal at “L”. In this case, the outputsignal from the inverter IV15 becomes “H” to connect the bit line BLt tothe node N via the transistor Q29. On the other hand, the gate G4provides an output signal at “H”, which turns the output signal from theinverter IV16 to “L”. This prevents the transistor Q30 from turning onand keeps the bit line BLc on the precharged voltage VDD.

As the boost enable signal boost_en and the write enable signal WE areboth at “L” before writing, the boot strap circuit 3 discharges the nodeA and the node N to 0 V via the transistors Q28, Q29. When the writeenable signal WE is turned to “H” to start writing, the transistor Q26turns on to start charging the node A from the supply voltage VDD viathe transistor Q26 and the transistor Q25 already turned on. Thetransistors Q25, Q26 are herein provided as a charge circuit for thecapacitor C_boost.

When the boost enable signal boost_en turns from “L” to “H”, thetransistor Q28 turns off in the boot strap circuit 3. In addition, thetransistor Q24 turns on to bring the potential on the node A from thecharged voltage to the ground voltage 0 V. At this time, the capacitivecoupling with the capacitor C_boost shifts the potential on the node Nalso in the negative direction. If the node A is charged up to thevoltage VDD, the capacitive coupling with the capacitor C_boost lowersthe node N from 0 V to around a voltage, −VDD. Thereafter, in accordancewith the ratio between the capacitance C_bl on the bit line BLt and thecapacitance on the capacitor C_boost in the boot strap circuit 3,charges are redistributed to determine the potential level Vbl on thebit line BLt as represented by the expression 2 in the first embodiment.

Thus, the bit line BLt of the bit line pair BL is brought to thenegative potential and the bit line BLc to the supply voltage VDD. Thepotentials on the bit lines BLt, BLc are fed via the transfertransistors Q5, Q6 in the SRAM cell SC to the inverters IV1, IV2 towrite data in the SRAM cell SC.

[Effect]

In the SRAM of the present embodiment, the node N is at 0 V when theboost enable signal boost_en is at “L”. Therefore, in the write buffercircuit 4, it is not required to switch between the NMOS transistoroperative to discharge the bit line pair BL to 0 V and the NMOStransistor operative to connect the bit line pair BL with the node N andshift it to the negative potential. This makes it possible to simplifythe configuration of the write buffer circuit 4 and reduce the chiparea.

Fourth Embodiment

A fourth embodiment of the present invention is described next withreference to FIG. 9 and so forth. FIG. 9 is a circuit diagram showing aconfiguration of a semiconductor memory device according to the fourthembodiment of the present invention. FIG. 9 selectively showsconfigurations of the boot strap circuit 3 and the write buffer circuit4 only.

[Configuration]

In the semiconductor memory device according to the present embodimentthe parts having the same configurations as those in the SRAM of thefirst and second embodiments are denoted with the same referencenumerals and omitted from the description. The SRAM according to thepresent embodiment differs from the first and second embodiments inconfigurations of the boot strap circuit 3 and the write buffer circuit4. In the SRAM of the present embodiment the inverter IV6 is shown ascontained in the boot strap circuit 3.

In the boot strap circuit 3 according to the present embodiment theinverters IV6-IV12, the transistors Q10-Q13 and the boot strap capacitorC_boost have the same configurations as those in the boot strap circuit3 of the first embodiment. The boot strap circuit 3 according to thepresent embodiment includes a PMOS transistor Q31 and an NMOS transistorQ32 connected between the inverter IV9 and the gate terminal of thetransistor Q10, different from the first embodiment. The transistorsQ31, Q32 are connected between the supply line VDD and the ground lineVSS in series. The output terminal of the inverter IV9 is connected tothe gate of the transistor Q31. The connection node B between thetransistors Q31, Q32 is connected to the gate terminal of the transistorQ10 and to the gate terminal of the transistor Q32 as well.

The write buffer circuit 4 of the present embodiment includes invertersIV17-IV20, and NMOS transistors Q33, Q34. The boost enable signalboost_en is fed via the inverters IV17, IV18 to the gate of thetransistor Q33 and to the gate of the transistor Q34 via the inverterIV17. The transistor Q33 has a source connected to the node N in theboot strap circuit. The transistor Q34 has a source connected to theground line VSS. The inverters IV19, IV20 are connected between thesupply line VDD and the transistors Q33, Q34. The input terminals of theinverters are supplied with mutually different data signals DI, /DI. Theoutput terminals of the inverters IV19, IV20 are connected to the bitlines BLt, BLc, respectively.

[Operation]

The following description is given to data writing with the use of theboot strap circuit 3 and the write buffer circuit 4 of the presentembodiment shown in FIG. 9.

In accordance with the write data signals DI, /DI, the write buffercircuit 4 connects either of the pair of bit lines BL (for example, thebit line BLc when the data signal DI is at “H” and /DI at “L”) to thesupply line VDD at the start of writing to precharge it to the voltageVDD. The boost enable signal boost_en is at “L” at the start of writingand thus the transistor Q34 turns on to discharge the bit line BLt to 0V.

In the boot strap circuit 3, the boost enable signal boost_en is at “L”before writing. Thus, the node A at one end of the capacitor C_boost isbrought to the voltage VDD via the inverters IV6-IV8. The write enablesignal WE is also at “L”. Thus, the node N at the other end isshort-circuited with the node A via the transistors Q10, Q11 and broughtto the voltage VDD. When the write enable signal WE is turned to “H” tostart writing, the node A is made out of conduction with the node N, andthe transistors Q12, Q13 turn on to discharge the node N.

When the write enable signal WE is at “H”, the transistor Q31 turns onto bring the voltage on the node N to the voltage VDD. If the supplyvoltage VDD is lower and the potential level of the voltage VDD appliedto the gate and drain of the transistor Q32 is lower than the thresholdvoltage Vth (Q32) of the transistor Q32, the transistor Q32 cannot turnon. In that case, the voltage VDD is applied to the gate terminal of thetransistor Q10 to turn off the transistor Q10.

On the other hand, if the supply voltage VDD is higher and the potentiallevel of the voltage VDD applied to the gate and drain of the transistorQ32 is higher than the threshold voltage Vth (Q32) of the transistorQ32, the transistor Q32 turns on. Therefore, the voltage applied to thegate terminal of the transistor Q10 descends to around Vth (Q32). Whenthe drain-gate voltage VDD−Vth (Q32) of the transistor Q10 becomes lowerthan the threshold voltage Vth (Q10) of the transistor Q10, thetransistor Q10 turns on. The condition for turning on the transistor Q10is represented as follows using the absolute value of the thresholdvoltage Vth (Q10) of the transistor Q10.VDD−Vth(Q32)>|Vth(Q10)|∴VDD>Vth(Q32)+|Vth(Q10)|  [Expression 5]

Namely, if the supply voltage VDD is higher than Vth(Q32)+|Vth(Q10)|,the transistor Q10 turns on. After the start of writing, the transistorsQ12, Q13 turn on to discharge the node N. In this case, if thetransistor Q10 has turned on, the reduction in the potential on the nodeN is made slower. The transistors Q10, Q31, Q32 are provided as apotential control circuit, which varies the rate of discharging the nodeN in accordance with the value of the supply voltage VDD to vary thevalue of the negative potential applied to the bit line BLt.

When the boost enable signal boost_en turns from “L” to “H”, in thewrite buffer circuit 4 the transistor Q34 turns off and the transistorQ33 connected to the node N in the boot strap circuit 3 turns oninstead. In the boot strap circuit 3 the potential on the node A variesfrom the supply voltage VDD to the ground voltage 0 V. At this time, thecapacitive coupling with the capacitor C_bost varies the potential onthe node N in the negative direction as well. Thereafter, in accordancewith the ratio between the capacitance C_bl on the bit line BLt and thecapacitance on the capacitor C_boost in the boot strap circuit 3,charges are redistributed to bring the potential level Vbl on the bitline BLt to the negative potential.

Thus, the bit line BLt of the bit line pair BL is brought to thenegative potential, and the bit line BLc to the supply voltage. Thepotentials on the bit lines BLt, BLc are fed via the transfertransistors Q5, Q6 in the SRAM cell SC to the inverters IV1, IV2 in theSRAM cell SC to write data in the SRAM cell SC.

[Effect]

FIG. 10 is a graph showing a relation between the supply voltage and thebit line potential in the SRAM according to the present embodiment. FIG.10 shows variations in the negative potential Vbl on the bit line BLt onwriting while the supply voltage VDD is varied from 0.8 V to 1.2 V. Thecomparison example in FIG. 10 shows an example in driving the boot strapcircuit, after the node N surely descends to 0 V, without using the bootstrap circuit 3 according to the present embodiment.

In the boot strap circuit 3, when the potential on the node A variesfrom the supply voltage VDD to the ground voltage 0 V, the capacitivecoupling with the capacitor C_boost lowers the potential on the node N.Namely, if the supply voltage VDD has a larger value, the potential onthe node N may possibly descend largely and apply an excessive negativepotential to the bit line BL. Therefore, as shown in FIG. 10, in theSRAM of the comparison example, the higher the supply voltage VDD, thelower the value of the bit line potential Vbl becomes. In general, fromthe viewpoint of reliability, the gate-source voltage available on thetransfer transistor in the SRAM cell SC is limited. Therefore, it isrequired to set the value of the negative potential on the bit line BLtolerable for the available supply voltage VDD applied to the gateterminal of the transfer transistor. If the supply voltage VDD islowered, the value of the negative potential on the bit line BLt is madesmaller in accordance with the supply voltage VDD. This causes a problembecause the negative potential sufficient to improve the writecharacteristic cannot be ensured at the time of low voltage.

On the other hand, in the SRAM of the present embodiment, if the valueof the supply voltage VDD becomes larger than a certain value, thereduction in the potential on the node N after the start of writingbecomes slower. In the SRAM of the present embodiment, as the value ofthe supply voltage VDD becomes larger than a certain value, thereduction in the potential on the node N can be suppressedcorrespondingly. Thereafter, even if the capacitive coupling with thecapacitor C_boost lowers the potential on the node N, the potential Vblon the bit line BLt can be prevented from lowering much. As a result,the lower the supply voltage VDD, the lower the value of the bit linepotential Vbl becomes as shown in FIG. 10.

In FIG. 10, the bit line potential Vbl in the present embodiment andthat in the comparison example are compared such that they becomeidentical at the time of low voltage (VDD=0.8 V). If the gate-sourcevoltage on the transfer transistor is set constant from the viewpoint ofreliability, the SRAM of the present embodiment makes it possible to seta larger amount of boost at the time of low voltage than the comparisonexample.

Fifth Embodiment

A fifth embodiment of the present invention is described next withreference to FIG. 11 and so forth. FIG. 11 is a block diagram showing aconfiguration of a semiconductor memory device according to the fifthembodiment of the present invention. FIG. 11 selectively shows onlyconfigurations of the boot strap circuit 3 and a voltage sense circuit 5operative to control operation of the boot strap circuit 3.

[Configuration]

The SRAM of the present embodiment includes a voltage sense circuit 5operative to decide whether the supply voltage VDD is lower than acertain voltage. The voltage sense circuit 5 includes, for example, areference voltage generator circuit comprising a band-gap referencecircuit, and an op-amp operative to compare the reference voltagegenerated from the reference voltage generator circuit with the supplyvoltage VDD. The voltage sense circuit 5 provides a signal lvdd, whichbecomes “L” when the supply voltage VDD is higher than the referencevoltage and “H” when the former is lower than the latter.

The boot strap circuit 3 receives the boost enable signal boost_en andthe signal lvdd via an AND gate G9. Namely, the boot strap circuit 3 isactivated only when the supply voltage VDD is lower than a certainpotential and inactivated when the supply voltage VDD is higher than thecertain potential.

[Effect]

As described in the fourth embodiment, if the supply voltage VDD has alarger value, the potential on the node N may descend largely and applyan excessive negative potential to the bitline BL possibly. In the SRAMof the present embodiment, however, if the supply voltage VDD is higherthan a certain potential, the boot strap circuit 3 does not operate togenerate a negative voltage. Thus, it is possible to set the potentiallevel of the negative potential applied to the bit line at the time oflow voltage without constraints of the breakdown voltage of the transfertransistor in the SRAM cell SC when the supply voltage VDD is a highvoltage.

[Others]

The embodiments of the invention have been described above though thepresent invention is not limited to these embodiments but rather can begiven various modifications, additions and so forth without departingfrom the scope and spirit of the invention. For example, the negativepotential applied from the boot strap circuit 3 has such a thresholdthat is a value not higher than the breakdown voltage of the transfertransistor used in the SRAM cell SC even if the highest supply voltageof the use conditions for the SRAM is used. This makes it possible toset an appropriate amount of boost in the boot strap circuit.

In the fourth and fifth embodiments, the replica write buffer circuit 2of the first embodiment is used together with the boot strap circuit 3though the configuration for lowering the potential level of thenegative potential applied to the bit line as the supply voltage VDDdescends may also be used in general boot strap circuits.

1. A semiconductor memory device, comprising: a memory cell arrayincluding a plurality of word lines, a plurality of bit line pairscontaining a first bit line and a second bit line intersecting said wordlines, and a plurality of memory cells connected at the intersections ofsaid plurality of word lines and said plurality of bit line pairs; aplurality of replica bit lines formed in the same manner as said firstand second bit lines; a write buffer circuit operative to drive saidfirst or second bit line to the ground voltage on writing data to saidmemory cell; a replica write buffer circuit operative to drive saidreplica bit lines to the ground voltage by substantially the samedriving force as that of said write buffer circuit; and a boot strapcircuit operative to drive said first or second bit line currentlydriven to the ground voltage further to a negative potential at a timingwhen the potential on said replica bit lines reaches a certain value. 2.The semiconductor memory device according to claim 1, further comprisingan inverter circuit operative to activate a boost enable signal when itdetects that the potential on said replica bit lines reaches the certainvalue, wherein the capacitance of said replica bit lines issubstantially double the capacitance of said first or second bit line,wherein said certain value is substantially ½ the voltage value of thesupply voltage, wherein said boot strap circuit controls the timing ofdriving said first or second bit line to the negative potential based onsaid boost enable signal.
 3. The semiconductor memory device accordingto claim 1, further comprising a dummy cell connected to said replicabit lines and having substantially the same configuration as said memorycell, wherein said dummy cell is connected to a dummy word line that isto be selected at the same time as said word line on writing, whereinsaid dummy cell discharges said replica bit lines after said dummy wordline is selected.
 4. The semiconductor memory device according to claim3, wherein said bootstrap circuit shifts the negative potential appliedto either of said first or second bit line on writing to a lowerpotential as the threshold voltage of a transistor contained in saidmemory cell ascends.
 5. The semiconductor memory device according toclaim 2, wherein said boot strap circuit includes a capacitor elementhaving one terminal connectable to said first or second bit line basedon said boost enable signal, and a capacitor discharge circuit operativeto discharge one terminal of said capacitor element until said boostenable signal is activated after the beginning of writing by said writebuffer circuit, wherein said boot strap circuit connects said oneterminal of said capacitor element to said first or second bit line whensaid boost enable signal is activated, and discharges the other terminalof said capacitor element to drive said first or second bit line to thenegative potential.
 6. The semiconductor memory device according toclaim 5, wherein said boot strap circuit keeps substantially constantthe potential level of the negative potential generated therein,regardless of the length of said bit line pair.
 7. The semiconductormemory device according to claim 5, further comprising a dummy cellconnected to said replica bit lines and having substantially the sameconfiguration as said memory cell, wherein said dummy cell is connectedto a dummy word line that is to be selected at the same time as saidword line on writing, wherein said dummy cell discharges said replicabit lines after said dummy word line is selected.
 8. The semiconductormemory device according to claim 2, wherein said boot strap circuitincludes a capacitor element having one terminal connectable to saidfirst or second bit line based on said boost enable signal, and acapacitor charge circuit operative to charge the other terminal of saidcapacitor element until said boost enable signal is activated after thebeginning of writing by said write buffer circuit, wherein said bootstrap circuit connects said one terminal of said capacitor element tosaid first or second bit line when said boost enable signal isactivated, and discharges the other terminal of said capacitor elementto drive said first or second bit line to the negative potential.
 9. Thesemiconductor memory device according to claim 8, wherein said bootstrap circuit keeps substantially constant the potential level of thenegative potential generated therein, regardless of the length of saidbit line pair.
 10. The semiconductor memory device according to claim 8,further comprising a dummy cell connected to said replica bit lines andhaving substantially the same configuration as said memory cell, whereinsaid dummy cell is connected to a dummy word line that is to be selectedat the same time as said word line on writing, wherein said dummy celldischarges said replica bit lines after said dummy word line isselected.
 11. The semiconductor memory device according to claim 1,wherein said boot strap circuit uses a value not higher than thebreakdown voltage of a transistor contained in said memory cell as thethreshold voltage to control the negative potential.
 12. Thesemiconductor memory device according to claim 1, wherein said memorycell is an SRAM cell including a first and a second inverter havingmutually cross-connected input terminals and output terminals, eachinverter containing a PMOS transistor and an NMOS transistor, a firsttransfer transistor connected between the output terminal of said firstinverter and said first bit line and having a gate connected to saidword line, and a second transfer transistor connected between the outputterminal of said second inverter and said second bit line and having agate connected to said word line.
 13. The semiconductor memory deviceaccording to claim 1, wherein said boot strap circuit includes apotential control circuit operative to vary the value of the negativepotential applied to said first or second bit line in accordance withthe voltage value of the supply voltage, wherein said potential controlcircuit makes the negative potential larger in the negative direction asthe voltage value of the supply voltage descends.
 14. The semiconductormemory device according to claim 13, further comprising an invertercircuit operative to activate a boost enable signal when it detects thatthe potential on said replica bit lines reaches a certain value, whereinsaid boot strap circuit includes a capacitor element having one terminalconnectable to said first or second bit line based on said boost enablesignal, and a capacitor discharge circuit operative to discharge oneterminal of said capacitor element until said boost enable signal isactivated after the beginning of writing by said write buffer circuit,wherein said potential control circuit varies the discharge rate at oneterminal of said capacitor element in accordance with the voltage valueof the supply voltage, wherein said boot strap circuit connects said oneterminal of said capacitor element to said first or second bit line whensaid boost enable signal is activated, and discharges the other terminalof said capacitor element to drive said first or second bit line to thenegative potential.
 15. The semiconductor memory device according toclaim 13, wherein said potential control circuit includes a first NMOStransistor having a source terminal connected to the ground potential,and a gate terminal and a drain terminal connected in common, a firstPMOS transistor having a source terminal connected to the power source,a drain terminal connected to the drain terminal and the gate terminalof said first NMOS transistor, and controlled on writing to turn on, anda second PMOS transistor having a gate terminal connected to the gateterminal and the drain terminal of said first NMOS transistor and thedrain terminal of said first PMOS transistor, a source terminal suppliedwith the supply voltage, and a drain terminal connected to one terminalof said capacitor element.
 16. The semiconductor memory device accordingto claim 1, further comprising a voltage sense circuit operative tosense if the voltage value of the supply voltage is lower than a certainvoltage value to provide a control signal for controlling operation ofsaid boot strap circuit, wherein said boot strap circuit drives saidfirst or second bit line to the negative potential, based on saidcontrol signal, if the voltage value of the supply voltage is lower thanthe certain voltage value.
 17. A semiconductor memory device,comprising: a memory cell array including a plurality of word lines, aplurality of bit line pairs containing a first bit line and a second bitline intersecting said word lines, and a plurality of memory cellsconnected at the intersections of said plurality of word lines and saidplurality of bit line pairs; a write buffer circuit operative to drivesaid first or second bit line to the ground voltage on writing data tosaid memory cell; and a boot strap circuit operative to drive said firstor second bit line currently driven to the ground voltage further to anegative potential at a certain timing, wherein said boot strap circuitincludes a potential control circuit operative to vary the value of thenegative potential applied to said first or second bit line inaccordance with the voltage value of the supply voltage, wherein saidpotential control circuit makes the negative potential larger in thenegative direction as the voltage value of the supply voltage descends.18. The semiconductor memory device according to claim 17, wherein saidboot strap circuit includes a capacitor element having one terminalconnectable to said first or second bit line at said certain timing, anda capacitor discharge circuit operative to discharge one terminal ofsaid capacitor element until said certain timing after the beginning ofwriting by said write buffer circuit, wherein said potential controlcircuit varies the discharge rate at one terminal of said capacitorelement in accordance with the voltage value of the supply voltage,wherein said boot strap circuit discharges the other terminal of saidcapacitor element to drive said first or second bit line to the negativepotential.
 19. The semiconductor memory device according to claim 17,wherein said potential control circuit includes a first NMOS transistorhaving a source terminal connected to the ground potential, and a gateterminal and a drain terminal connected in common, a first PMOStransistor having a source terminal connected to the power source, adrain terminal connected to the drain terminal and the gate terminal ofsaid first NMOS transistor, and controlled on writing to turn on, and asecond PMOS transistor having a gate terminal connected to the gateterminal and the drain terminal of said first NMOS transistor and thedrain terminal of said first PMOS transistor, a source terminal suppliedwith the supply voltage, and a drain terminal connected to one terminalof said capacitor element.
 20. A semiconductor memory device,comprising: a memory cell array including a plurality of word lines, aplurality of bit line pairs containing a first bit line and a second bitline intersecting said word lines, and a plurality of memory cellsconnected at the intersections of said plurality of word lines and saidplurality of bit line pairs; a write buffer circuit operative to drivesaid first or second bit line to the ground voltage on writing data tosaid memory cell; a boot strap circuit operative to drive said first orsecond bit line currently driven to the ground voltage further to anegative potential at a certain timing; and a voltage sense circuitoperative to sense if the voltage value of the supply voltage is lowerthan a certain voltage value to provide a control signal for controllingoperation of said boot strap circuit, wherein said boot strap circuitdrives said first or second bit line to the negative potential, based onsaid control signal, if the voltage value of the supply voltage is lowerthan the certain voltage value.